Due to the growing complexity of modern Integrated Circuits (ICs), there is a need for automated circuit design methods. Recent years have seen rising research in hardware design language generation to facilitate the design process. In this work, we propose a Verilog generation framework, BetterV, which fine-tunes the large language models (LLMs) on processed domain-specific datasets and incorporates generative discriminators for guidance on particular design demands. The Verilog modules are collected, filtered and processed from internet to form a clean and abundant dataset. Instruct-tuning methods are specially designed to fine-tuned the LLMs to understand the knowledge about Verilog. Furthermore, data are augmented to enrich the training set and also used to train a generative discriminator on particular downstream task, which leads a guidance for the LLMs to optimize the Verilog implementation. BetterV has the ability to generate syntactically and functionally correct Verilog, which can outperform GPT-4 on the VerilogEval-machine benchmark. With the help of task-specific generative discriminator, BetterV can achieve remarkable improvement on various electronic design automation (EDA) downstream tasks, including the netlist node reduction for synthesis and verification runtime reduction with Boolean Satisfiability (SAT) solving.
The Rise of Automated Circuit Design and BetterV’s Verilog Generation Framework
In recent years, the growing complexity of Integrated Circuits (ICs) has presented a need for automated circuit design methods. This has led to an increase in research focused on hardware design language generation to streamline the design process. In response to this demand, a Verilog generation framework called BetterV has been developed.
BetterV takes advantage of large language models (LLMs) that have been fine-tuned on processed domain-specific datasets. These datasets are generated by collecting, filtering, and processing Verilog modules from the internet, resulting in a clean and abundant dataset for training the LLMs.
To ensure the LLMs have a strong understanding of Verilog, instruct-tuning methods have been specially designed to fine-tune them. This process enhances the models’ grasp of Verilog knowledge, enabling them to generate syntactically and functionally correct Verilog code.
Moreover, data augmentation techniques are employed to enrich the training set. By augmenting the dataset, BetterV improves its ability to generate high-quality Verilog implementations. Additionally, this augmented data is used to train a generative discriminator. The discriminator provides guidance to the LLMs when optimizing the Verilog implementation for specific design demands.
One notable achievement of BetterV is its performance on the VerilogEval-machine benchmark, where it outperforms GPT-4. This showcases its ability to generate Verilog code that surpasses current state-of-the-art models in evaluating Verilog designs.
Furthermore, the multi-disciplinary nature of BetterV becomes evident when considering its impact on electronic design automation (EDA) downstream tasks. With the assistance of task-specific generative discriminators, BetterV demonstrates remarkable improvements in various EDA tasks.
For example, BetterV excels in netlist node reduction for synthesis, which can optimize the overall circuit layout and improve efficiency. By reducing the number of nodes in the netlist, BetterV streamlines the synthesis process, leading to more optimized designs.
Additionally, BetterV proves its worth in reducing verification runtime through Boolean Satisfiability (SAT) solving. By leveraging the generative discriminator’s guidance, BetterV can fine-tune the Verilog implementation to minimize SAT solving time, resulting in faster and more efficient verification processes.
In conclusion, BetterV’s Verilog generation framework addresses the need for automated circuit design in today’s complex ICs. Its integration of large language models, instruct-tuning methods, data augmentation, and a task-specific generative discriminator provides powerful tools for producing high-quality Verilog code. With its success on the VerilogEval-machine benchmark and its improvements in various EDA downstream tasks, BetterV showcases the multi-disciplinary nature of its contributions to the field of automated circuit design.